1. Field of the Invention
The present invention relates to a DC/DC converter and a controlling method thereof, and more particularly to a DC/DC converter of current-mode control.
2. Description of the Related Art
A DC/DC converter is a device for converting a applied DC voltage into a higher/lower DC voltage, and is used in various fields.
FIG. 1 is a circuit diagram exemplifying a conventional DC/DC converter. This DC/DC converter is operated with a PWM (Pulse Width Modulation) method, and sometimes referred to as a switching regulator. This DC/DC converter monitors an electric current flowing through an inductor, and regulates an output DC voltage based on the monitored current.
A switch SW is, for example, a MOS transistor, to which an input voltage V.sub.in is applied. The switch SW is turned on (ON state) or turned off (OFF state) depending on the state of a flip-flop 101. An inductor current IL flowing via an inductor L approximately linearly increases while the switch SW is in the ON state (ramp-up), and approximately linearly decreases while the switch SW is in the OFF state (ramp-down).
A diode D is arranged to make an electric current flow when the switch SW is in the OFF state. Also the configuration where a MOS transistor, etc. is used as a replacement of the diode D is known. The configuration where a MOS transistor, etc. is used as a replacement of the diode D is sometimes called a synchronously rectifying type. An output capacitor C.sub.out is arranged to smooth an output voltage V.sub.out.
In this DC/DC converter, the output voltage V.sub.out and the inductor current IL are used as feedback signals. An error amplifier 102 amplifies a difference between the output voltage V.sub.out (more precisely, a voltage obtained by dividing the output voltage V.sub.out with a resistor network composed of resistors R1 and R2) and a predetermined reference voltage V.sub.ref, and outputs the result of the amplification as an instruction value signal I.sub.cnt. A comparator 103 makes a comparison between the inductor current IL (more precisely, the voltage corresponding to the inductor current IL) and the instruction value signal I.sub.cnt output from the error amplifier 102. Then, the comparator 103 outputs the result of the comparison as a reset signal.
An oscillator 104 generates a set signal. The set signal is a pulse signal which is synchronous with an oscillation frequency of the oscillator 104. The set signal is input to the set terminal of the flip-flop 101 via an AND gate (an AND gate one of whose inputs is a negative logic) 105, while the reset signal from the comparator 103 is input to the reset terminal of the flip-flop 101.
The operations of the DC/DC converter having the above described configuration are explained below. Upon receipt of the set pulse from the oscillator 104, the flip-flip 101 is set. When the flip-flop 101 enters the set state, the switch SW is turned on, which leads to an increase in the inductor current IL. When the inductor current IL reaches the instruction value signal I.sub.cnt being the output of the error amplifier 102, the output of the comparator 103 is changed from "L" to "H". The output of the comparator 103 is applied to the reset terminal of the flip-flop 101.
Upon receipt of "H" at the reset terminal, the flip-flop 101 is reset. When the flip-flop 101 enters the reset state, the switch SW is turned off, which leads to a decrease in the inductor current IL. The next set pulse is then generated by the oscillator 104. When the set pulse is input to the set terminal of the flip-flop 101, the above described operations are repeated.
As described above, in the DC/DC converter shown in FIG. 1, the output voltage V.sub.out is held constant by controlling the inductor current IL with the instruction value signal I.sub.cnt which varies according to the output voltage V.sub.out. The output voltage to be held by this DC/DC converter is determined by the reference voltage V.sub.ref.
In the above described DC/DC converter, the state of the switch SW is switched from ON to OFF, when the inductor current IL reaches the instruction value signal I.sub.cnt as described above. Actually, however, the A switch SW is turned off after a predetermined amount of time elapses from when the inductor current IL reaches the instruction value signal I.sub.cnt. This is because of a delay in a circuit.
FIG. 2 explains the operations and the problems of the DC/DC converter shown in FIG. 1.
The set pulse of the set signal is output at a time T.sub.1, and input to the set terminal of the flop-flop 101. Here, the AND gate 105 is assumed to be open at the time T.sub.1.
The flip-flop 101 is set according to the set pulse. When the flip-flop 101 enters the set state, the switch SW is turned on, which leads to an increase in the inductor current IL, as described above. When the inductor current IL reaches the instruction value signal I.sub.cnt at a time T.sub.2, the output (reset signal) of the comparator 103 is changed from "L" to "H" at the time T.sub.2.
When the reset signal becomes "H", the flip-flop 101 enters the reset state. As a result, the switch SW is turned off. When the switch SW is turned off, the inductor current IL starts to decrease.
As described above, however, a delay occurs on the path over which the signals are transmitted. In this case, the comparator 103 and the flip-flop 101 cause the delay. Therefore, the switch SW is actually turned off after a predetermined amount of time (delay time td) elapses from when the inductor current IL reaches the instruction value signal I.sub.cnt at the time T.sub.2. As a result, the inductor current IL continues to increase between the times T.sub.2 and T.sub.3. That is to say, the inductor current IL becomes larger than needed due to the above described delay.
The increasing rate (di/dt) of the inductor current IL while the switch SW is in the ON state depends on the inductance of the inductor L, the input voltage V.sub.in, and the output voltage V.sub.out. EQU di/dt.varies.(V.sub.in -V.sub.out)/L (1)
However, the increasing rate of the inductor current IL while the switch SW is in the ON state has been becoming higher in recent years. That is, in these years, the voltage required by a load (such as a CPU used in a personal computer, etc.) has been dropping year by year. As a result, the output voltage V.sub.out of the DC/DC converter is set to a lower value more frequently than before. In this case, the increasing rate of the inductor current IL becomes higher as is evident from the above provided equation (1). Additionally, the inductance of the inductor L must be made smaller as the current required by a load becomes larger. Also in this case, the increasing rate of the inductor current IL rises as is evident from the above provided equation (1).
If the increasing rate of the inductor current IL is high, the inductor current IL sharply increases. As a result, the inductor current IL becomes much larger than the instruction value I.sub.cnt at the timing (time T.sub.3) when the switch SW is turned off.
When the switch SW is turned off at the time T.sub.3, the inductor IL gradually decreases thereafter. The decreasing rate (di/dt) of the inductor current IL is represented by the following equation (2). Particularly, when the output voltage V.sub.out of the DC/DC converter is set to a small value, the decreasing rate is low. EQU di/dt.varies.-V.sub.out /L (2)
The oscillator 104 generates the next set pulse at a time T.sub.4. The inductor current IL, however, is much larger than the instruction value I.sub.cnt at the time T.sub.3, and its decreasing rate IL after the time T.sub.3 is low. Accordingly, the inductor current IL may sometimes remain larger than the instruction value I.sub.cnt.
If the inductor current IL is larger than the instruction value I.sub.cnt, the output (reset signal) of the comparator 103 is "H". Consequently, the AND gate 105 remains closed according to the reset signal at the time T.sub.4.
While the AND gate 105 is closed, the set pulse generated by the oscillator 104 is blocked by the AND gate 105. That is to say, the flip-flop 101 cannot receive the set pulse that should be received at the time T.sub.4 if the AND gate 105 were open. Therefore, the inductor current IL continues to decrease after the time T.sub.4.
The oscillator 104 further generates the next set pulse at a time T.sub.5. At this time, the inductor current IL is smaller than the instruction value I.sub.cnt. If the inductor current IL is smaller than the instruction value I.sub.cnt, the output (reset signal) of the comparator 103 is "L", which opens the AND gate 105. Namely, the set pulse can pass through the AND gate 105 at the time T.sub.5. Accordingly, the flip-flop 101 enters the set state according to the set pulse at the time T.sub.5, and the switch SW is turned on. Thereafter, the inductor current IL continues to increase until the flip-flop 101 is reset.
The above described DC/DC converter gives a higher priority to the reset signal over the set signal as the input signal of the flip-flop 101. This is intended to prevent an overcurrent, etc., and is implemented by the AND gate 105.
In the conventional DC/DC converter, the set pulse for turning on the switch SW is sometimes blocked by an influence of a circuit delay as described above. In the example shown in FIG. 2, the switch SW is not turned on at the time T.sub.4 although it should be originally turned on at the times T.sub.1, T.sub.4, T.sub.5, . . . .
If the switching interval becomes longer as described above, the ripple of the output voltage V.sub.out naturally becomes larger. Since the allowable value of the ripple, which is demanded by the load, has recently become strict, it is vital to reduce the ripple of the output voltage of the DC/DC converter.
Additionally, when the switching frequency (or a switching interval) of the switch SW changes, the frequency of noise caused by the switching also varies with its change. To suppress the noise output from the DC/DC converter in this case, the rejection bandwidth of the filter for eliminating noise must be broadened. However, because such a filter costs high or its size is large, it is not preferable.